Each CPLD family members has more than one ways of I/O pin termination available to avoid pins from floating at high-impedance and causing noise and exorbitant power dissipation.

Each CPLD family members has more than one ways of I/O pin termination available to avoid pins from floating at high-impedance and causing noise and exorbitant power dissipation.

Controlling I/O Termination

This topic contains details about configuring I/O.

These termination techniques range from the weak resistive pull-up circuit, the p r keeper circuit ( also known as a « bus hold » circuit) and user-configurable ground pins. These termination features, where current, are controllable on either a per-pin or whole unit basis, with respect to the CPLD family members. Termination on I/O pins found in your design and termination on unused I/O pins are controlled separately.

Whenever a pad is perhaps not driven either externally or by the CPLD macrocell, the resistive pull-up circuit, if enabled, keeps a top logic state to stop the pad from floating. Whenever a low logic degree is placed on the pad, the pull-up continues to supply handful of present. Continuer la lecture de « Each CPLD family members has more than one ways of I/O pin termination available to avoid pins from floating at high-impedance and causing noise and exorbitant power dissipation. »